Projects
05 projects5-Stage Pipelined RISC-V CPU
KAIST · SystemVerilog, ModelSim, EDA Playground
FPGA/ASIC-synthesizable 5-stage processor with full testbench suite. Directly relevant to FPGA-based high-speed data acquisition pipelines (OCT systems).
- Verified 100% testbench pass rate (40/40 cases) across sort and forloop programs at 14,722 cycles / 147 µs simulation time
- Designed hazard detection and data-forwarding unit — eliminates all RAW stalls across IF/ID/EX/MEM/WB pipeline stages
- Real debugging evidence: caught forwarding bug mid-development (test #6 failed, 0xfe8 vs 0xed8), traced via waveform, corrected — verified 40/40
- Synthesizable to both FPGA and ASIC targets — verified with EDA Playground timing constraint analysis
Sort testbench — 40/40 passed. Tests #1–40 verified at 147,335 ns, 14,722 cycles.
ModelSim waveform — sort program. CLK, pipeline registers (IF/ID → MEM/WB), forwarding signals.
Waveform — forloop program. All 5 pipeline stage instructions, PC write, ID/EX flush across 450 ns.
Debugging evidence. Test #6 failed: 0xfe8 vs expected 0xed8. Mis-forwarded operand, traced and corrected.
Ultra-Low-Power Smartwatch Firmware
KAIST · C, nRF5 SDK, Arduino Nano 33 BLE (nRF52840)
End-to-end embedded hardware project from schematic study and part selection through power-optimized firmware to a wearable prototype — the same skillset needed for implantable and surgical device electronics.
- Reduced average current draw to 85 µA (DMM-measured) by implementing IMU duty cycling, OLED auto-sleep, and coordinated I2C sensor polling intervals on nRF52840
- Part selection and I2C integration: LSM6DS step counter, APDS-9960 gesture sensor, SSD1306 OLED display — all multiplexed over I2C with independent sleep windows
- Implemented BLE GATT server firmware (nRF5 SDK, C) — service/characteristic discovery, notifications, and client-server data sync following BLE specification
- Studied nRF52840 schematic and pin configuration (NINA-B3X) — GPIO mapping, SWD debug interface, QSPI, NFC, and power rail assignments
- Designed and 3D-printed wearable enclosure with wrist strap, component stacking, and USB access for flashing
Working prototype on wrist. OLED displaying live step count (step: 0019), Arduino Nano 33 BLE board, I2C wiring. Black 3D-printed wrist enclosure.
Device design. Arduino Nano 33 BLE front/rear, battery holders, and exploded-view 3D-printed enclosure with wrist strap mount.
BLE GATT architecture. Server (wristband) — client (smartphone) model: service discovery, characteristic discovery, CCCD, and read/write/subscribe flows.
nRF52840 schematic (NINA-B3X). GPIO pin mapping, SWD debug interface, QSPI, NFC/GPIO28-29, reset, power rails — studied for firmware pin assignments.
▶ Live demo
Smartwatch_firmware.mp4 — live demo of gesture UI, OLED display, step counter, and BLE sync on the wearable prototype
Multi-Sensor Agricultural IoT Network
AXInvent · IoT Device Engineer Intern · Daejeon, South Korea
Full hardware lifecycle — part selection to field deployment. Master/slave LoRa mesh for real-time environmental monitoring, built, debugged, and validated outdoors across multiple field tests.
- Part selection: CO2, soil moisture, wind anemometer, rainfall, soil temp sensors — evaluated for outdoor endurance, power budget, and I2C/UART compatibility
- System-level schematic design: defined pin mapping for all sensor interfaces, power distribution rails (5V/DC battery), LoRa module wiring across Arduino slave nodes
- Hardware bring-up: verified I2C bus timing with oscilloscope, traced and resolved NULL sensor readings (visible in test logs) by correcting pull-up resistor values
- 3D enclosure design in Fusion 360 — weatherproof housing for master and slave nodes, optimized for cable routing and field serviceability
- Pipeline: slave Arduinos → LoRa → master → Raspberry Pi 4 → gRPC/HTTP/2 → server; validated with live sensor acquisition logs
Device internals. Master node (Arduino + RPi4 + CO2 + sensors) and slave node (Arduino + DC battery + LoRa antenna) in weatherproof enclosures.
Field deployment — bring-up validation. Master + slave nodes deployed, verifying LoRa range, sensor comms, and battery endurance.
Communication pipeline. Slave Arduinos → LoRa → Master → USB → RPi4 → gRPC/HTTP/2 → AXInvent server.
Field test data. Air temp 27.6°C, wind 3.2 m/s, CO2 633–639 ppm. NULL rows = fault isolation targets during bring-up debugging.
Digital Clock FSM in SystemVerilog
KAIST · SystemVerilog, EDA Playground
RTL implementation with three verified modes: normal time advance, adjustment, and alarm set/clear. FSMs, flip-flops, counters, and MUX trees verified with waveform analysis.
- Verified alarm control FSM (set/turn-off inputs, alarm output) — all state transitions validated via ModelSim testbenches
- Verified hours/minutes/seconds tracking across all three operating modes with dedicated waveforms
Normal advance — seconds, minutes, hours incrementing correctly with clock.
Adjustment mode — new hour/minute values loaded into output registers.
Alarm set/clear — o_alarm asserted at target, cleared on demand.
Sub-mW Neuromorphic Wildfire Detection Node
QAIST · Research Assistant · Almaty, Kazakhstan
Field-deployable sensor hardware with neuromorphic chips targeting sub-mW operation — analogous to always-on, battery-constrained sensing in implantable neural devices.
- Targeting sub-mW operation — relevant to power-critical implantable and surgical electronics
- Defined electrical and software interface specs between neuromorphic sensing units and wireless mesh
- Coordinating requirements with KAIST researchers and industry partners across sensing, power, and communication domains
Curriculum Vitae
Arslan Kenbayev — CV (2026)
↓ Download PDFHardware Skills
design
Part selection, system-level schematic design, analog/digital circuit assembly, 3D enclosure design (Fusion 360, SolidWorks)
bring-up
Hardware bring-up, oscilloscope waveform analysis, DMM power rail verification, I2C/SPI/UART protocol debugging
embedded
C, C++, nRF5 SDK / Segger Studio, Arduino, BLE GATT, sensor integration, power state machines
digital design
SystemVerilog, Verilog, FSM synthesis, 5-stage pipelined CPU, testbench verification, ModelSim, EDA Playground
platforms
Arduino Nano 33 BLE (nRF52840), Raspberry Pi 4, Nvidia Jetson, RISC-V, nRF5 SDK
lab
Oscilloscope, DMM, power supplies, I-V characterization, OLED thin-film device fabrication
Experience
Aug 2025 –
Present
Present
Research Assistant — Hardware
QAIST · Almaty, Kazakhstan
Sub-mW neuromorphic IoT sensor node development. Electrical/software interface specification for wireless mesh-network integration with industry partners.
May 2025 –
Mar 2026
Mar 2026
IoT Device Engineer Intern
AXInvent · Daejeon, South Korea
Full hardware lifecycle: part selection, schematic design, PCB assembly, Fusion 360 enclosure, bring-up, field deployment. I2C/SPI/UART debugging with oscilloscope/DMM.
May –
Aug 2025
Aug 2025
Semiconductor Engineer Intern
KAIST IOEL Lab · Daejeon, South Korea
Organic OLED fabrication from CO2-derived compounds. I-V sweep characterization, layer composition tuning for healthcare electronics.
Jul –
Sep 2024
Sep 2024
Automation Engineer Intern
AAEngineering · Almaty, Kazakhstan
Sensor design validation in SolidWorks, RF/network topology analysis, automated control logic design.
Feb –
Jun 2024
Jun 2024
Software Engineer Intern
KAIST CIS Lab · Daejeon, South Korea
Expanded KakaoMap vehicle route-planning by implementing the CCH algorithm under Prof. Heejin Ahn.